Design of FD-SOI-specific True Random Number Generator


TRNGs are the essential block of any cryptographic system. Current standards, such as AIS-31, require a stochastic model, which directly relates the model of the physical source of randomness to the entropy of the generated random bits. TRNGs are benchmarked based on their throughput, efficiency and robustness. As such, FD-SOI (Fully Depleted Silicon on Insulator) is a technology well known for its advantages in terms of consumption, but also for the adaptability of its characteristics granted by its unique back bias control acting as a second gate. This PhD position aims to extend the use of this back gate by studying the opportunities offered by an integrated management of the back gate. By applying a voltage, the BOX allows the adjustment of characteristics at a transistor level. This technique called back biasing, enables the fine-tuning of characteristics and has thus far not been used in the design of security primitives. This technique will be implemented for a FD-SOI specific TRNG based on coherent sampling. Though the novelty and the relevance of the FD-SOI based approach is clear, and motivations to go toward coherent sampling architectures for TRNG have been documented in the literature, the objective of the PhD student will be to bring experimental demonstration, with the support of simulation and modelling of these specific architectures. This will be made possible by a first version of ASIC samples already available at the start of the PhD and the design (by the PhD student) of another ASIC.

Master en Electronique et/ou Microélectronique, Sécurité Matérielle, Systèmes Embarqués

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