Design and construction of a snubber circuits associated with a power transistors in order to reduce disturbances during fast switching.

The thesis topic is aligned with the European Common Interest Project IPCEI ME/CT, which aims to enhance the value of the European semiconductor sector. It particularly investigates protection systems for direct current (DC) electrical networks against power overloads, short circuits, and electric arc incidents. These complex systems rely on power transistors to manage controlled disconnection of the electrical network, incorporating either separate functions or combined functions with a DC-DC converter. Despite the abundant literature on the subject, it showcases a variety of approaches and configurations depending on the DC voltage and power levels involved. This project focuses on the activation of DC lines under severe conditions, initially at 400V (low-voltage DC, LVDC) and subsequently at 800V (medium-voltage DC, MVDC). In the LVDC context, the emergence of GaN HEMT transistors (Gallium Nitride, with a breakdown voltage greater than 650V) has enabled the study of how well these components perform in line disconnection tasks. The rapid switching of the transistor necessitates precise control of the switching trajectory to ensure that the transistor operates within the safety limits specified by the manufacturer. Typically, this involves a snubber circuit for switching assistance. If an overvoltage cannot be avoided, a clamping device is added in parallel to the transistor. Experimental validation of such setups is quite challenging, especially when transistors are used in series or parallel, which motivates the development of alternatives that do not rely on a snubber circuit. However, due to the relative fragility of GaN transistors, this approach is not optimal. Therefore, the project looks at integrating a switching assistance solution within the GaN transistor package. The production of the transistors and snubbers will utilize the facilities and techniques of the CEA-Leti cleanrooms, with microelectronic manufacturing processes optimized to allow their integration with silicon trench capacities, enabling co-integration with GaN transistors. The components will be assembled after being encapsulated. Switching tests will initially be conducted within an inverter arm to assess various snubber circuit designs, switching frequencies, speeds, and temperatures. An ultra-fast metrological approach will be developed alongside the transistor design to enable measurements without compromising functionality. In a later phase, the most promising solutions will also be validated within a back-to-back setup, in the particularly challenging case of opening an inductive DC line.