Join CEA LETI for an exciting technological journey! Immerse yourself in the world of III V based transistors integrated on compatible CMOS circuits for 6 G future communications This thesis offers the chance to work on a ambitious project, with potential to continue into a thesis If youapos;re curious, innovative, and eager for a challenge, this opportunity is perfect for you! As the consumption of digital content continues to grow, we can foresee that 6 G communication systems will have to find more capacity to support the increase in traffic New Sub THz frequencies based systems are a huge opportunity to increase data rate but are very challenging to build and maturate the power amplifier required to transmit a signal will have to offer sufficient power and energy efficiency which is not obtained with actual silicon technology InP based HBTs (Heterojunction Bipolar Transistors) developed on large Silicon substrates have the potential to meet the requirements and be integrated as close as possible to the CMOS circuits to enable minimal system/interconnect losses Sb based semiconductors for GaAsSb HBT are emerging as highly promising materials, especially for its electrical properties to integrate the Base layer of the Transistor It is therefore necessary to produce high performance electrical contacts on this type of semiconductor while remaining compatible with the manufacturing processes of the Si Fab technology platforms Throughout this thesis, you will gain a broad spectrum of knowledge, beneficiate from the rich technical environment of the 300 200 mm clean room and the nano characterization platform You will collaborate with multidisciplinary teams to develop a deep understanding of the ohmic contacts and analyse existing measurements Several apsects of the metal (Ni or Ti p GaAs 1 x Sb x contact will be investigated •Identify wet and plasma solutions allowing the GaAsSb native oxide removing without damaging the surface with XPS and AFM •Characterize GaAs 1 x Sb x epitaxy doping level (Hall effect, SIMS, TEM) •Understand the phase sequence during annealing between the semiconductor and the metal with XRD and Tof SIMS Manage this intermetallic alloys formation to not deteriorate the contact interface (TEM image associated) •Evaluate electrical contact properties using TLM structures Measurement of the specific contact resistivity, sheet resistance of the semiconductor ant transfer length associated The student will be a motive force to perform electrical tests on an automatic prober
Ingénieur ou master en physique ou chimie
Talent impulse, the scientific and technical job board of CEA's Technology Research Division
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