Research Engineer in optimization and Design Space Exploration for Next-Generation Computing Systems H/F

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IN SUMMARY, WHAT DO WE OFFER YOU? We are looking for an Research Engineer in optimization and Design Space Exploration for Next-Generation Computing Systems. This position in fixed-term contact is based at Nano-Innov (CEA Paris-Saclay), Essonne (91). This position is available as soon as possible. Context Modern computing systems ranging from high-performance computing (HPC) to embedded AI and automotive platforms face increasingly complex and interdependent design challenges. These systems must meet strict constraints on performance, power, area, cost, and reliability, all while adapting to rapidly evolving workloads and technologies. The design process involves both hardware architecture choices (e.g., cores, memory hierarchy, accelerators, interconnects) and software-level decisions (e.g., task mapping, scheduling, compiler optimizations), which together lead to a combinatorial explosion of possible configurations. Exploring these vast and heterogeneous design spaces is computationally demanding, often requiring costly simulations and automated optimization loops to efficiently navigate trade-offs and identify optimal or near-optimal solutions. To address these challenges, CEA has developed A-DECA (Architecture Design Exploration and Configuration Automation), an in-house Electronic Design Automation (EDA) framework. A-DECA provides a modular, flexible, and multi-objective design space exploration environment for architecture-level decision making. It enables early, automated evaluation of hardware/software configurations for HPC, AI, and automotive systems. Research Objectives You will contribute to the development of next-generation optimization methodologies integrated into the A-DECA framework. The focus is on exploration strategies that go beyond traditional techniques such as linear programming or deterministic solvers. You will work on cutting-edge methods including: Bayesian optimization Surrogate modeling to accelerate evaluation of costly simulations Genetic algorithms and other evolutionary techniques to generate a diverse set of high-performing solutions. You will design and implement new optimization techniques capable of handling: Extremely large design spaces with many interacting variables Multi-objective trade-offs (performance, power, area, sustainability, etc.) Complex constraints and architectural decisions typical of real-world electronic systems Your work will enable the automatic generation of optimized and diversified architecture configurations, and provide insightful trade-off analysis across the design space. Validation & Applications The methods developed will be tested and validated on: Various benchmarks to assess performance, scalability, and robustness Real-world case studies from national and European R&D projects Industrial use cases including architecture exploration for HPC and AI accelerators Cross-domain applications such as automotive  #CEA-List ; #LI-CB1 ; #Ingénieure

Nous accueillons les candidatures de profils disposant d’une solide formation en optimisation, en intelligence artificielle ou en génie informatique, et motivés par des défis interdisciplinaires. Compétences et centres d’intérêt recherchés : Recherche opérationnelle et optimisation combinatoire (ex. : solveurs Gurobi, CPLEX, Hexaly) Optimisation bayésienne, algorithmes évolutionnaires ou méthodes hybrides Optimisation multi-objectifs et sous contraintes Modélisation approchée, méta-modélisation ou apprentissage statistique Excellentes compétences en programmation, notamment en Python et/ou C++ Une familiarité avec les outils EDA, les architectures numériques ou les systèmes embarqués est un plus. Conformément aux engagements du CEA en faveur de l’intégration des personnes en situation de handicap, ce poste est ouvert à toutes et tous. Le CEA propose des aménagements et/ou des modalités d’organisation pour favoriser l’inclusion des travailleurs en situation de handicap.

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